{"id":16484,"date":"2025-05-28T15:39:59","date_gmt":"2025-05-28T12:39:59","guid":{"rendered":"https:\/\/www.weebit-nano.com\/?p=16484"},"modified":"2025-06-25T14:00:33","modified_gmt":"2025-06-25T11:00:33","slug":"relaxation-aware-programming-in-reramevaluating-and-optimizing-write-termination","status":"publish","type":"post","link":"https:\/\/www.weebit-nano.com\/relaxation-aware-programming-in-reramevaluating-and-optimizing-write-termination\/","title":{"rendered":"Relaxation-Aware Programming in ReRAM:
Evaluating and Optimizing Write Termination"},"content":{"rendered":"

\"\"<\/p>\n

Resistive RAM<\/a> (ReRAM<\/a> or RRAM<\/a>) is the strongest candidate for next-generation non-volatile memory<\/a> (NVM<\/a>), combining fast switching speeds with low power consumption. New techniques for managing a memory phenomenon called \u2018relaxation\u2019 are making ReRAM more predictable \u2014 and easier to specify for real-world applications.<\/p>\n

What is the relaxation problem in memory? Short-term conductance drift \u2013 known as \u2018relaxation\u2019 \u2013 presents a challenge for memory stability, especially in neuromorphic computing and multi-bit storage.<\/p>\n

At the 2025 International Memory Workshop (IMW)<\/a>, a team from CEA-Leti<\/a>, CEA-List<\/a> and Weebit<\/a> presented a poster session, \u201cRelaxation-Aware Programming in RRAM: Evaluating and Optimizing Write Termination.\u201d The team reported that Write Termination (WT), a widely used energy-saving technique, can make these relaxation effects worse.<\/p>\n

So what can be done? Our team proposed a solution: a modest programming voltage overdrive that curbs drift without sacrificing the efficiency advantages of the WT technique.<\/p>\n

 <\/p>\n

Energy Savings Versus Stability<\/strong><\/h4>\n

Write Termination improves programming efficiency by halting the SET (write) operation once the target current is reached, instead of using a fixed-duration pulse. This reduces both energy use and access times<\/a>, supporting better endurance across ReRAM arrays.<\/p>\n

It\u2019s desirable, but problematic in action.<\/p>\n

Tests on a 128kb ReRAM macro showed that unmodified WT increases conductance drift by about 50% compared to constant-duration programming.<\/p>\n

\"\"<\/p>\n

In these tests, temperature amplified the effect: at 125\u00b0C, the memory window narrowed by 76% under WT, compared to a fixed SET pulse. Even at room temperature, degradation reached 31%.<\/p>\n

Such drift risks destabilizing systems that depend on tight resistance margins, including neuromorphic processors<\/a> and multi-level cell (MLC) storage schemes, where minor shifts can translate into computation errors or data loss.<\/p>\n

The experiments used a testchip fabricated on 130nm CMOS<\/a>, integrating the ReRAM array with a RISC-V subsystem for fine-grained programming control and data capture.<\/p>\n

Conductance relaxation was tracked from microseconds to over 10,000 seconds post-programming. A high-speed embedded SRAM<\/a> buffered short-term readouts, allowing detailed monitoring from 1\u00b5s to 1 second, while longer-term behavior was captured with staggered reads.<\/p>\n

This statistically robust setup enabled precise analysis of both early and late-stage relaxation dynamics.<\/p>\n

To measure stability, the researchers used a metric called the three-sigma memory window (MW\u2083\u03c3). It looks at how tightly the memory cells<\/a> hold their high and low resistance states, while ignoring extreme outliers.<\/p>\n

When this window gets narrower, the difference between a \u201c0\u201d and a \u201c1\u201d becomes harder to detect \u2014 making it easier for errors to creep in during reads.<\/p>\n

By focusing on MW\u2083\u03c3, the team wasn\u2019t just looking at averages \u2014 they were measuring how reliably the memory performs under real-world conditions, where even small variations can cause problems.<\/p>\n

 <\/p>\n

Addressing Relaxation with Voltage Overdrive<\/strong><\/h4>\n

Voltage overdrive is the practice of applying a slightly higher voltage than the minimum required to trigger a specific operation in a memory cell \u2014 in this case, the SET operation in ReRAM.<\/p>\n

Write Termination cuts the SET pulse short as soon as the target current is reached. That saves energy, but it also means some memory cells are just barely SET. They\u2019re fragile \u2014 sitting near the edge of their intended resistance range. That\u2019s where relaxation drift kicks in: over time, conductance slips back toward its original state.<\/p>\n

So, the team asked a logical question:<\/p>\n

\u201cWhat if we give the cell just a bit more voltage \u2014 enough to push it more firmly into its new state, but not so much that we burn energy or damage endurance?\u201d<\/p>\n

Instead of discarding WT, the team increased the SET voltage by 0.2 Arbitrary Units (AU) above the minimum requirement.<\/p>\n

Key results:<\/strong><\/h4>\n