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In AI inference, trained models apply their knowledge to make predictions and decisions. To achieve lower latency and better security, the world is transitioning steadily towards performing AI inference at the edge \u2013 without sending data back and forth to the cloud \u2013 for a wide range of applications<\/a>.<\/p>\n Because edge devices are often small, battery-powered, and resource-constrained, it\u2019s important that the computing resources enabling this process and the associated memories are ultra-low-power and low-cost. This is a challenge for AI workloads, which are known to be power-hungry.<\/p>\n The industry has been making progress towards lower power computation largely by moving to more advanced process nodes. This enables more performance with greater energy efficiency in smaller silicon<\/a> area. However, non-volatile memories<\/a> (NVMs) haven\u2019t been able to scale to advanced nodes along with logic. Today we see advanced chips<\/a> in process nodes of 3nm. At the same time, embedded flash memory is unable to scale below 28nm. This means that NVM and AI engines are often manufactured at very different process nodes and can\u2019t be integrated on the same silicon die.<\/p>\n This is one of many reasons why the industry is exploring new memory technologies<\/a> like Weebit ReRAM<\/a> (RRAM<\/a>).<\/p>\n <\/p>\n Neural Network coefficients (often referred to as NN weights), which are used for computations by the inference engine, need to be stored in an NVM<\/a>, so that when the system is powered-on these coefficients are available for compute workloads. Because it\u2019s not possible to integrate flash<\/a> and an AI engine on one die below 28nm, it is standard practice to implement a two-die solution, with one die at a small process node used for computing, and the other die at a larger process node used for storing the coefficients. These two dies are then either integrated in a single package or in two separate packages. Either way, such a two-die solution is more expensive and has a bigger footprint. Also, copying the coefficients from an external flash to an on-chip SRAM in the AI chip is very power hungry and creates latencies. In addition, the fact that the coefficients are moved from one chip to the other creates a security risk, as it is easy to eavesdrop this communication.<\/p>\n The ideal solution for edge AI computing from power, latency, cost and security perspectives is a single die that hosts both memory and compute.<\/p>\n <\/p>\n Embedded ReRAM is the logical alternative to flash for edge AI. ReRAM is significantly more energy efficient than flash, and it provides better endurance<\/a> and faster program time. Since it is scalable to advanced processes, ReRAM enables a true one-chip solution, with NVM and computing integrated on the same die<\/a>.<\/p>\n ReRAM-enabled SoC<\/a>s are less expensive to manufacture because they only require two additional masks in the manufacturing flow, while flash requires 10 or even more such masks. Embedding ReRAM into an AI SoC would eliminate the need for off-chip flash devices and replace most of the large on-chip SRAM<\/a> used to temporarily store the NN weights. Since the technology is non-volatile, the system can boot much faster as there is no need to wait for loading the AI model and firmware from external NVM, and the security risk is removed. ReRAM is also much denser than SRAM, so more memory can be integrated on-chip to support larger neural networks for the same die size and cost, while enabling more advanced AI algorithms.<\/p>\n A new demonstration showcases the advantages of Weebit ReRAM-powered edge AI computing. Developed through a collaboration between Weebit and Embedded AI Systems Pte. Ltd. (EMASS)<\/a>, a subsidiary of Nanoveu<\/a>, the gesture recognition demo shows Weebit ReRAM working with EMASS\u2019s energy-efficient AI SoC, the EMASS ECS-DOT. The demo emphasizes the ultra-low-power consumption of ReRAM and its ability to enable instant wake-up AI operations. In the real world, such a system could be used to detect driver activity for advanced driver safety systems, or it could be used for safety\/surveillance, robotics, and many other applications.<\/p>\n ECS-DOT is an edge AI chip manufactured in a 22nm process that delivers significant energy efficiency and cost advantages, with best-in-class AI capacity. In the demo, ECS-DOT loads the neural network weights from Weebit ReRAM where they are being stored. As noted earlier, this is a powerful feature of ReRAM \u2013 it can be used to replace the large on-chip SRAM to store the NN weights, as well as the CPU<\/a> firmware.<\/p>\n Weebit ReRAM isn\u2019t yet integrated into the ECS-DOT SoC, so the proof-of-concept demo shows a two-chip solution with the 22nm Weebit demo chip communicating with the EMASS chip over an SPI bus. In an end solution, the ReRAM would be integrated on-chip, eliminating latency, cost and security risks, and demonstrating even lower power consumption. Such integration can enhance system performance and also ensure scalability and sustainability, paving the way for smarter, more autonomous edge devices.<\/p>\n Above: ultra-low-power ReRAM based gesture recognition systemThe need for a single-die solution<\/strong><\/h4>\n
A scalable, single-chip solution with ReRAM<\/strong><\/h4>\n
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<\/p>\nNew Demo: ReRAM for ultra-low-power edge AI<\/strong><\/h4>\n
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\nwith Weebit ReRAM and EMASS AI SoC<\/em><\/p>\n